1. Field of the Invention
The present invention relates to a method of forming electric wiring in a semiconductor device. More particularly, the present invention relates to a method of forming electric wiring using a dual damascene process in which contacts and conductive lines may be formed simultaneously.
2. Description of the Related Art
Great strides are being made in semiconductor technology as the use of information media, such as computers, continues to increase. To be functionally efficient, semiconductor devices should be operated at a high speed and have a large storage capacity. Accordingly, semiconductor manufacturing technologies are continually being developed to improve the integration degree, reliability and response time of semiconductor devices. One semiconductor technology in particular, a process for forming electric wiring in a semiconductor device, is subject to strict requirements.
Aluminum, which has a low contact resistance that facilitates the electric wiring process, has conventionally been used to form electric wiring in semiconductor devices. If used in highly integrated semiconductor devices, however, aluminum wiring structures may cause various problems, such as a junction spike failure and electromigration. Additionally, a material having a lower resistance than that of aluminum is preferable in order to improve the response speed of the semiconductor device.
Consequently, copper, having a lower resistance and superior electromigration characteristics, is often used together with a low dielectric insulation layer in order to form electric wiring. Copper is rapidly dispersed in silicon and various metal layers, however, so copper has not been adapted for a conventional photolithography process. For this reason, a damascene process is used for forming electric wiring with copper. When forming electric wiring using the damascene process, a dual damascene process wherein conductive lines and contacts may be formed simultaneously, is preferably used for economical reasons.
The dual damascene structure has a via hole where a contact connected to a lower conductor is formed and a trench where a conductive line is formed. The dual damascene structure is achieved by performing one of following etching processes. In a first etching process, the trench is formed after forming the via hole (via-first-forming method). In a second etching process, the via hole is formed after forming the trench (trench-first-forming method). In the third etching process, the via hole and the trench are simultaneously formed (buried-trench-forming method).
The above processes are discriminated from each other by the order in which the via hole and trench are formed in the photolithography and etching processes. The process may be properly selected according to the size of the trench and via hole, the misalign degree of the trench and via hole, etc.
Among the above processes, the via-first-forming method is primarily used because it can simplify the dual damascene structure and reduce misalignment of the trench and via hole.
FIGS. 1A to 1D illustrate sectional views showing a conventional method of forming an electric wiring using a dual damascene process.
Referring to FIG. 1A, a first insulation layer 10, having a via hole or a trench filled with conductive material, is formed on a semiconductor substrate (not shown). Accordingly, an upper surface of a conductive pattern 10a formed by the conductive material filling the via hole or the trench is exposed at a predetermined portion of an upper surface of the first insulation layer 10.
Then, an etch stop layer 12 is formed on the first insulation layer 10. A second insulation layer 14 and a third insulation layer 16 are sequentially formed on the etch stop layer 12. The third insulation layer 16 is formed of a material having a lower dielectric constant than that of the second insulation layer 14, and generally has a dielectric constant (k) below 3.5.
Via holes for connecting conductors to each other are formed in the second insulation layer 14 by the next process. The second insulation layer 14 insulates the via holes from each other. In addition, trenches for forming upper conductive lines are formed in the third insulation layer 16. The third insulation layer 16 insulates the upper conductive lines from each other. Accordingly, the third insulation layer 16 includes a low dielectric material for preventing an increase in capacitance between adjacent upper conductive lines. Generally, the third insulation layer 16 includes carbon or a carbon compound, which is a low dielectric material.
Referring to FIG. 1B, a via hole 18 is formed by etching predetermined portions of the third and second insulation layers 16a and 14a, such that a predetermined portion of the etch stop layer 12 positioned on the conductive pattern 10a of the first insulation layer 10 may be exposed. Therefore, the conductive pattern 10a is positioned below a bottom of the etch stop layer 12 which is exposed at a lower portion of the via hole 18.
Referring to FIG. 1C, a linear trench 20 partially overlapping the via hole 18 is formed by etching a predetermined portion of the third insulation layer 16b. The trench 20 includes the via hole 18 and is formed wider than the via hole 18. At the trench 20, the upper conductive line is formed by the next process.
In order to etch the third insulation layer 16b including carbon or a carbon compound, a plasma etching process is carried out using CxFy gas together with mixing gas including oxygen gas and nitrogen gas. Etching gas for etching the third insulation layer 16b has a low etching selectivity with respect to the etch stop layer 12a. For this reason, when etching the third insulation layer 16b, the etch stop layer 12a exposed at the lower portion of the via hole 18b is etched simultaneously.
If the upper portion of the conductive pattern 10a positioned below the etch stop layer 12a is exposed due to the etching of the etch stop layer 12a, high energy plasma collides with the upper surface of the exposed conductive pattern 10a. As a result, a lower portion of the conductive pattern 10a, where the contact is to be formed, may be damaged.
Referring to FIG. 1D, a conductive material 22 is used to fill the via hole and trench 20 after removing the etch stop layer 12a remaining in the lower portion of the via hole 18b. Then, a polishing process is carried out such that the conductive material 22 remains only in the via hole 18b and the trench 20, thereby forming the electric wiring.
When forming the electric wiring according to the above-mentioned conventional process, the etch stop layer 12a formed at the lower portion of the via hole 18b may be etched when etching the trench 20 for forming the conductive line, so that the lower conductive pattern 10a becomes damaged. For this reason, it is difficult to achieve a contact having a low resistance.
To solve the problems described above, there has been suggested a method for etching a trench after forming an anti-reflection layer consisting of an organic material in a state that a via hole has been formed. However, in accordance with the method described above, a portion of the third insulation layer to be etched is frequently not etched, thereby causing failure of the semiconductor device.
In addition, the prior art discloses a method of forming a trench in which a spin-on-glass layer is formed after forming a via hole. Then, after forming the trench by etching the third insulation layer, the spin-on-glass layer is removed. However, although using the spin-on-glass layer when etching the trench in this method may protect the lower layer, it is difficult to remove the spin-on-glass layer in a subsequent process. In addition, since the etch stop layer indicating an end point of the etch is not provided when the via hole is formed, a lower conductive pattern may be damaged by the plasma.
The present invention has been made to overcome the deficiencies of the prior art as described above. Therefore, it is a feature of an embodiment of the present invention to provide a method of forming electric wiring using a dual damascene process such that damage to a lower conductive pattern may be prevented and a low contact resistance may be achieved.
To provide this and other features of the present invention, a method of forming a wiring of a semiconductor device is provided, including: forming a first insulation layer having a hole or a first trench filled with a conductive material on a semiconductor substrate; sequentially forming a first etch stop layer including a non-oxide based insulating material having carbon or a carbon compound and a second insulation layer including an oxide based insulating material on the first insulation layer; forming a third insulation layer including the oxide based insulating material on the second insulation layer; forming a capping layer including a non-carbonic oxide based insulating material on the third insulation layer; forming a via hole by etching predetermined portions of the capping layer, the third insulation layer and the second insulation layer in such a manner that a part of the first etch stop layer corresponding to an upper portion of the hole or the trench filled with conductive material is exposed; forming a photoresist pattern on the capping layer having the via hole so as to form a linear trench including the via hole; partially etching the capping layer using the photoresist pattern as an etching mask, the capping layer being reacted with an etching gas used for etching the capping layer to form a polymer layer on the first etch stop layer for protecting the first etch stop layer; forming a second trench by sequentially etching the remaining capping layer and the third insulation layer using the photoresist pattern as an etching mask; removing the photoresist pattern and the polymer layer; removing the first etch stop layer exposed at a lower portion of the via hole; and filling a resulting structure with a conductive material.
According to the method of the present invention, when the capping layer is partially etched, polymer is sufficiently formed on the first etch stop layer by being reacted with the etching gas used for etching the capping layer. When the second trench is etched, the first etch stop layer cannot be etched together with the second trench due to the presence of the polymer, so damage to the lower conductive pattern is prevented.